Capacitors in electrical integrated circuits (ICs) are typically incorporated between the interconnect layers of a semiconductor wafer in order to maximize the use of the space between the interconnect layers. The capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction, as the conductors of the interconnect layers are metal in construction. MIM capacitors may be used to store a charge in a variety of semiconductor devices, that may be utilized in the IC. For example, such MIM structures are one of the key devices in radio-frequency (RF). mixed-signal integrated circuit, and DRAM application.
Conventional MIM structures consume a relatively large percentage of the surface area of a semiconductor wafer or chip because they are typically constructed as a large flat structure formed by a low dielectric constant (k) silicon dioxide or nitride capacitor dielectric layer sandwiched between upper and lower metal electrodes, positioned parallel to the wafer surface. There is an ongoing challenge to maintain sufficiently high storage capacitance despite decreasing capacitor area, since capacitance is generally a function of electrode area. In order to reduce the area of these structures, yet obtain higher capacitance density per unit size, the prior art has attempted a few different approaches.
One approach has been to replace the low-k material used for the dielectric layer with high-k materials, such as Al2O3, HfO, and Ta2O5, having a k value higher than 9. However, such high-k materials do not adhere well to the metal electrodes, which are still relatively large, thereby leading to delaminations in the MIM structures. Another conventional approach of increasing capacitance has been is to reduce dielectric thickness. Capacitance is set forth in equation (1),
                    C        =                  k          *                      A            t                                              (        1        )            where C=capacitance, k=dielectric constant, A=electrode area, and t=dielectric thickness).
An even more advantageous approach for gaining capacitance (per device size) would be to shrink the dielectric thickness and employ a high-k material simultaneously. Unfortunately, high-k materials are often incompatible with the idea of decreasing dielectric thickness due to the issue of leakage current. More specifically, as high-k dielectrics are made thinner, the propensity of leakage or “tunneling” current from electrode to electrode across the dielectric increases. Accordingly, an MIM capacitor structure is needed that utilizes wafer area more efficiently than conventional MIM capacitor structures, while using high-k dielectrics without the detrimental effects of leakage current.